AnandTech
Date: August 24, 2020
By: Andrei Frumusanu

At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the form of N5P and N4 process nodes.

Starting off with TSMC’s upcoming N5 process node which represents its 2nd generation deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) process node after the rarely used N7+ node (Used by the Kirin 990 SoC for example). TSMC has been in mass production for several months now as we’re expecting silicon shipping to customers at this moment with consumer products shipping this year – Apple’s next-generation SoCs being the likely first candidates for the node.

TSMC details that N5 currently is progressing with defect densities one quarter ahead of N7, with the new node having better yields at the time of mass production than both their predecessor major nodes N7 and N10, with a projected defect density that’s supposed to continue to improve past the historic trends of the last two generations.

The foundry is preparing a new N5P node that’s based on the current N5 process that extends its performance and power efficiency with a 5% speed gain and a 10% power reduction.
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